SEU Strategies for Virtex - 5 Devices

Xilinx® devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events. This application note introduces an SEU controller macro that can be included in any Virtex®-5 FPGA design to implement an SEU detection and correction scheme. This application note is also a useful tool in evaluating the different methods for addressing SEUs. Due to the infrequent and unpredictable nature of real SEUs, small scale testing of their effects and system verification is impractical. For this reason, the SEU controller macro can emulate an SEU by deliberately injecting an error into the FPGA configuration to confirm the subsequent detection and correction. Injection of errors can also be used to assess SEU mitigation circuits implemented in a design and to verify the claims made in this application note. This application note focuses on the Virtex-5 family, however, much of the discussion is also applicable to the Spartan®-6, Virtex-6, and Extended Spartan-3A families.